Release Note for Cilai/Caesar3/Cilai-FE Bootcode Firmware ================================================================= 57780, 57760, 57790, 57788 ---------------------------- Version 3.21 ---- 12/16/09 ---------------------------- 1. Problem: CQ44571 NAKs observed in PCIE trace after several hours of traffic throughput test. Cause: This issue is related to CQ39683. With CQ39683 workaround, NAKs is still observed over longer period of testing when there are more L0/L0s transition. With 0x7e70 bit[4:0] set to 0x09, the rate of NAK occurrence was reduced. Workaround: Set register 0x7e70 bit[4:0] = 0x09. ---------------------------- Version 3.20 ---- 11/05/09 ---------------------------- 1. Enhancement: CQ44207 Bootcode clear 0x3600 bit13 when PHY Auto Power-Down is disabled. ---------------------------- Version 3.19 ---- 6/05/09 ---------------------------- 1. Problem: CQ41770 can't enable pxe after programming in bootcode 3.18. Cause: Bootcode 3.18 grew too big and is encroaching upon the stack region. Fixed: Shrink code to fit. ---------------------------- Version 3.18 ---- 5/29/09 ---------------------------- 1. Problem: CQ39683 Cilai detects Receiver Error when the Link Transition between L0s/L0 Workaround: shorten the delay of the electrical idle signal from serdes a. write register 0x7e70 bit [4:0] with 0x0c during device initialization or device reset b. write all ones to register 0x110 (correctable error status). 2. Enhancement: Checked for Vmain present before access PCI Config Registers. ---------------------------- Version 3.17 ---- 5/18/09 ---------------------------- 1. Enhancement: Changed PCIe SerDes register values to the following to use low-power transmitter mode: 1. Register 0x15 in block 0x8610 = 0x47b. 2. Register 0x1A in block 0x8010 = 0x4038. ---------------------------- Version 3.16 ---- 3/16/09 ---------------------------- 1. Enhancement: CQ37694 Updated Serdes setting of L1 Exit Latency based on OTP HW configuration bits. Mode 3: Default 123 uS: Otp Bits = 11 (11) write 44c 241f8080 write 44c 24121d1f write 44c 24130c1f write 44c 241400ff write 44c 24171f00 Program bit 17:15 of Register D8 to 111 Mode 1: Default 64 uS: Otp Bits = 01 (10)(01) write 44c 241f8080 write 44c 24121d19 write 44c 24130c02 write 44c 24140096 write 44c 24170100 Program bit 17:15 of Register D8 to 110 Mode 0: Default 20-30 uS: Otp Bits = 00 (10) write 44c 241f8080 write 44c 24120219 write 44c 24130c02 write 44c 24140032 write 44c 24170100 Program bit 17:15 of Register D8 to 101 Mode 2: Default 40 uS: Otp Bits = 10 (01) (00) write 44c 241f8080 write 44c 24121919 write 44c 24130c02 write 44c 24140096 write 44c 24170100 Program bit 17:15 of Register D8 to 110 ---------------------------- Version 3.15 ---- 3/03/09 ---------------------------- 1. Problem: CQ39741 System can't wake up from LAN when do S1/S3 mode with 57760. Cause: Phase 1 bootcode for 57760 overlap the Stack region. Updating Stack will corrupt the Phase 1 bootcode. As a result, CPU will stop which will cause system can't wake up from LAN when do S1/S3 mode. Fixed: Reduce Phase 1 bootcode size for 57760 such that it will not overlap with the Stack region. 2. Problem: CQ39706 Bootcode 3.14 can wake up 57760 on linux system after SUT enter S5 mode Cause: Phase 1 bootcode for 57760 overlap the Stack region. Updating Stack will corrupt the Phase 1 bootcode. As a result, device may get reset when entering S5 mode and going to OOB state. Since OOB-WOL is enabled, the system will wake up after SUT enter S5 mode. Fixed: Reduce Phase 1 bootcode size for 57760 such that it will not overlap with the Stack region. 3. Enhancement: CQ 39508 update. Program the SWR based on OPT 138. 4. Problem: CQ39704 After 50 iterations of driver load/unload for each speed, 57760A1 failed to bring link up. Cause: Phase 1 bootcode for 57760 overlap the Stack region. Updating Stack will corrupt the Phase 1 bootcode. As a result, CPU may corrupt system data and cause device to disappear. Fixed: Reduce Phase 1 bootcode size for 57760 such that it will not overlap with the Stack region. ---------------------------- Version 3.14 ---- 2/24/09 ---------------------------- 1. Problem: CQ39672 Cilai legacy bootcode v3.13 will fail b57diag c2 test Cause: Phase 1 bootcode overlap the Stack region. Updating Stack will corrupt the Phase 1 bootcode. As a result, CPU will stop which cause b57diag C2 Test to fail. Fixed: Reduce Phase 1 bootcode size such that it will not overlap with the Stack region. ---------------------------- Version 3.13 ---- 2/23/09 ---------------------------- 1. Enhancement: Set Reg 0x4400 and Reg 0x4800 to 1 to initialize BufMgr and DMAR if BufMgr is not enabled. 2. Enhancement: CQ 39508 Program the SWR based on OPT 138. ---------------------------- Version 3.12 ---- 2/12/09 ---------------------------- 1. Problem: CQ39339 The Link drop to 10M immediately once NIC Battery Saving Mode in BACS is enabled with AC Power applied. Cause: The issue is due to the current default value of "DisablePowerSaving" is 0 which enabled the reverse nWay feature. The reverse nWay feature should not be enabled by default. Fixed: Changed the default value of "DisablePowerSaving" bit in NVRAM to 1 to disable the reverse nWay feature. 2. Problem: Bootcode drive GPIO_0 instead of GPIO_2 when switching power after setting up wol. Fixed: Bootcode will GPIO_2 when switching power after setting up wol. 3. Enhancement: Set Reg 0x4400 and Reg 0x4800 to 1 to initialize BufMgr and DMAR. 4. Enhancement: Sets GPHY exp 75 reg vdacctrl bit 0 in GPHY initialization --------------------------- Version 3.11 ---- 12/18/08 ---------------------------- 1. Enhancement: CQ39027 Reducing the L0s Exit Latency from 1 uS down to 704 nS. 1. Write 7e50 with 0x2c 2. Write 7e14 with 0x2c 3. Write 44c 241f8400 4. Write 44c 24170083 2. Enhancement: Disable GPHY APD by the following instructions when the "enable_auto_powerdown" configuration bit is cleared in NVRAM. wr 44c 0x243C941F < This disables DLL Power Down in APD by setting bit 2 in GPHY Register 1C at Shadow 0x5 wr 44c 0x243CA801 < This disables GPHY APD The current code will leave the registers in their default state when the "enable_auto_powerdown" configuration bit is cleared in NVRAM. ---------------------------- Version 3.10 ---- 12/16/08 ---------------------------- 1. Enhancement: Added new setting to improve the RX performance when L0s is Enabled. 1. Write 7e14 with 0x2c 2. Write 44c 241f8400 3. Write 44c 24170083 ---------------------------- Version 3.09 ---- 11/13/08 ---------------------------- 1. Enhancement: CQ38483 Modified power_present() to base on Reg 0x6804 instead of Reg 0x36c2. ---------------------------- Version 3.08 ---- 11/10/08 ---------------------------- 1. Enhancement: Changed the default value of Reg 0x364c to 0x4B to improve performance. 1. write 0x364c 0x4B ---------------------------- Version 3.07 ---- 10/17/08 ---------------------------- 1. Enhancement: Bootcode changes the VDDR Bias and enable Link Idle Mode. 1. write 44c 241f8400 2. write 44c 241a009d 3. write 7d54 7008 4. Enable Link Idle mode by setting bit 9 of Register 3600 ---------------------------- Version 3.06 ---- 10/07/08 ---------------------------- 1. Enhancement: CQ37796 Bootcode changes the PLL BW from 3-4MHz to 5-6Mhz. Write 44c 241f8080 Write 44c 241c001b ---------------------------- Version 3.05 ---- 10/07/08 ---------------------------- 1. Enhancement: CQ37694 Updated Serdes setting of L1 Exit Latency based on OTP HW configuration bits. Mode 3: Default 123 uS: Otp Bits = 11 write 44c 241f8080 write 44c 24121d1f write 44c 24130c1f write 44c 241400ff write 44c 24171f00 Program bit 17:15 of Register D8 to 111 Mode 2: Default 64 uS: Otp Bits = 01 write 44c 241f8080 write 44c 24121d19 write 44c 24130c02 write 44c 24140096 write 44c 24170100 Program bit 17:15 of Register D8 to 110 Mode 1: Default 20-40 uS: Otp Bits = 10 write 44c 241f8080 write 44c 24120219 write 44c 24130c02 write 44c 24140032 write 44c 24170100 Program bit 17:15 of Register D8 to 101 Mode 0: Default 40 uS: Otp Bits = 00 write 44c 241f8080 write 44c 24121919 write 44c 24130c02 write 44c 24140096 write 44c 24170100 Program bit 17:15 of Register D8 to 101 2. Enhancement: CQ 37711 Adjusted voltage for the 1.2V Rail to 1.20V instead of 1.233V by writing to the following registers: 1. Write 36a0 3e0 2. Write 36ac 41 ---------------------------- Version 3.04 ---- 10/06/08 ---------------------------- 1. Removed workaround: Extended L1 entry time to 4ms to address CQ37120 by writing Reg 0x7d28 with 0x182FFFA for A0 only. This workaround will be done by drivers. 2. Problem: CQ37549 In normal mission mode, Link Led and Spd1000 Led are always off. Cause: Uart Disable Bit (bit 4) in Reg 0x6808 was cleared by ROM loader. In addition, Bootcode and SBROM code will over write the Uart Disable Bit after setting up WOL in NIC mode. Fixed: Boot code will set Uart Disable Bit (bit 4) in Reg 0x6808 to support LED Mode and preserve the state of the Uart Disable Bit after setting up WOL in NIC mode. 3. Problem: 57780 WOL does not wake up system after unexpected shutdown. Cause: PME Enable Bit (bit 8) of Reg 0x4c is not set. Fixed: Set PME Enable Bit when setting up WOL. 4. Problem: CQ37691 Intermittently OTP commands were not executed when they are issued by the internal CPU. As the result the OTP cannot be accessed reliably. Cause: OTP block and the internal may be running in different clock speed. As a result, the OTP block may not be able to receive the commands issued by internal CPU. Workaround: Extend the OTP commands duration such that the OTP commands will not be missed. This issue will be fixed in B0. ---------------------------- Version 3.03 ---- 9/03/08 (Obsolete) ---------------------------- 1. Extended L1 entry time to 4ms to address CQ37120 by writing Reg 0x7d28 with 0x182FFFA for A0 only. ---------------------------- Version 3.02 ---- 7/09/2008 ---------------------------- 1. Modified otp_read function. 2. Updated code according to the SW Programming Guide v1. ---------------------------- Version 3.01 ---- 6/17/2008 ---------------------------- 1. Enabled ASF support for 57760. 2. Reduced RxMBuf size for 16K bytes to 13K bytes when ASF is enabled. 3. Enabled GPIOs by default. ---------------------------- Version 3.00 ---- 6/9/2008 ---------------------------- 1. Initial engineering release This is a branch of 5784 v3.35.